Illustration of 3rd party IP being used on a semiconductor chip.
May 2, 2023

Managing IP: Using External IP for Semiconductor Design

IP Lifecycle Management

Managing IP is at the heart of semiconductor design. But in today’s design environment, IPs are not just created by in-house hardware teams. Many organizations leverage external IP, also known as vendor IP or 3rd party IP, to be incorporated into a final design. It is important to set up an IP workflow for managing IP throughout the co-development process (releases, bug fixes, etc. from vendors) to maintain traceability throughout your product lifecycle. Read along or jump to the section that interests you most:

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What Is External IP or Third Party IP?

In the semiconductor world, IP refers to a component. External IP, also known as third party IP, is IP that is purchased from external vendors, such as Synopsys, Arm, etc. 

Designers may look at IP as a block for a specific project. This IP can be developed internally or acquired from an third party. External IP that is purchased from third party vendors is usually delivered via a download or tarball.

Considerations When Using External IP

Unlike internal IP, there are special considerations that your teams should be aware of. Vendors may have commercial or security considerations, such as restrictions on what projects it can be used in, who can view the IP, etc. It is important to set up your system and workflow to create permissions and notifications around access and use.

Also, when using 3rd party IP, it is often still in co-development. This means that you will be collaborating with the vendor on any updates. You will need to create a process to report bugs and run tests around any of the IP’s functionality and features. Collaborating with external team members can be difficult, but having a process in place will ensure that you can track how the IP evolves.

Learn How to Bypass External IP Bottlenecks and Design Chips in House 

Considering bringing chip design in-house to get to market faster? Learn how to evaluate the risks and ROI, plus start planning your IP-centric design methodology, by reading our In-House Chip Design Considerations white paper. 
 

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Managing IP Traceability

When using external IP, managing IP traceability is key. It is important that you can understand:

  • What versions are being used?
  • Who is using the IP? Where?
  • Who can see/edit these IPs?
  • What changes were made to the IP, by who, and when?

Having a single source of truth is critical. But not all systems can provide this level of information about their own internal IPs, let alone external IP. So how can you create a workflow and ensure traceability?

 

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Helix IPLM — A New Approach to Managing IP

Helix IPLM (formerly Methodics) is the first tool of its kind to center IP in your design workflow. This is because in Helix IPLM, anything can be considered an IP. For example, you can set up your system to include the following as IP:

  • Engineering environment/configurations
  • Design (WIP or Planned) IP
  • PDKs & libraries
  • Usage tracking
  • Extensions
  • Release management
  • Integrations
  • IP generators
  • And more!

This idea of IP is a departure from other development processes. Having an IP-centric workflow, and allowing everything to be versioned as IP, means that you have a meta-data trail that is traceable. You can simply add a property label within the system to identify vendor IP. When it comes to managing permissions and setting up events, Helix IPLM can protect down to the individual IP. You can also create permissions to restrict access and events so that you are notified when an IP changes.

Having a central platform for IP management, independent of your data management tool, provides full traceability and enhanced visibility into how an IP is used. This also creates an IP ecosystem or catalog that can be used for discovery. If another project has matching requirements, and the IP is available, it can easily be incorporated into other projects. As the IP continues to evolve, it can be branched and patched using the same processes as internal IPs.

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Join a discussion with our experts and your peers on a variety of topics impacting semiconductor design teams. Sign up for our monthly MUG — Helix User Group.

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Improve External IP Management

To get the most out of your investment in third party IP, it is important to manage it properly. Using Helix IPLM creates a flexible workflow that allows your teams to protect IP to prevent leakage and manage it across the lifecycle of products.

Helix IPLM is trusted by 9 of the 10 top semiconductor companies to help ensure that design teams are able to efficient, while maintaining full traceability and IP security while managing IP — no matter the source.

Connect with one of our IP experts to learn how Perforce can help you improve both internal and third party IP management and streamline your design process. You can get answers to your questions and gain access to evaluation resources to see how Helix IPLM can benefit your business.

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Note: This blog was first published in April 2022 and was updated for quality and accuracy in May 2023.

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