Accelerate Semiconductor Development with IP-Centric Design

Workspaces are central to SoC integration. It’s the point where IP and the rest of the design come together. Helix IPLM's advanced IP and data caching infrastructure reduces workspace creation time from hours to seconds — and dramatically decreases data storage requirements. So designers have instant access to the files and data they need. 

Administrators can track IP usage and development across the enterprise. And comprehensive controls enable admins to determine the design files, IPs, tool configurations, machine resource allocation, and other infrastructure components available to team members.

Helix IPLM provides a single source of truth for creating and managing your bill of materials (BoM). With a hierarchical BoM for hardware, software, and the platform, you get a complete view of the project, including all versions and dependencies. 

These versioned releases ensure quality through centralized management of IP integration rules and checkpoints. For example, you can define which range of hardware IP versions a software component is compatible with. So, if a hardware team upgrades, Helix IPLM will flag a compatibility mismatch.

Teams can even integrate planned and in-progress IPs in a Planning BoM to accelerate the design planning process and enable better build-or-buy decisions.

Data is key to making informed project decisions. Helix IPLM offers at-a-glance visibility of data through configurable dashboards, backed by a powerful data analytics platform. Default dashboard configurations are provided for common design tasks, such as IP qualification, IP release status, and IP usage information. And new widgets can easily be added through the user-friendly, visual widget editor.

Helix IPLM also includes a first-class RESTful API for custom dashboard development, including company specific reporting, industry compliance, or integration of existing corporate systems.

Helix IPLM automates the design release process, eliminating the risks associated with manually releasing a design. Hierarchical release mechanisms ensure that IP blocks are released in the correct order, based on design dependencies, for quality-driven release flows.

Helix IPLM also provides pre-release and post-release hooks and triggers to ensure no IPs are made available to others until they meet your organization's standards for IP Quality and maturity.

Helix IPLM ensures the highest level of security to protect critical IP assets from every angle. Fine-grained user permissions allow you to control IP access. And with end-to-end traceability from requirements to release, you can easily track IP usage across your entire IP catalog — and quickly identify vulnerabilities in released ICs.

Violating technology export control laws can result in millions of dollars in fines, on top of lost revenue and market setbacks caused by IP leakage. IPLM’s Geofencing feature ensures compliance and prevents IP leakage by restricting IPs and metadata in prohibited locations, regardless of access permissions.